The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a system and method to facilitate flexible scan testing of bus driver components.
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems include processors that have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include a variety of components including microelectronic integrated circuits. Efficient and reliable performance testing of integrated circuit (IC) chips is critical to assure the IC operates properly.
The complexity of commonly used integrated circuits has advanced dramatically and built in self test (BIST) diagnostics capability is essential for effective circuit testing, debugging, and maintenance. Modern BIST techniques typically include the insertion of a scan test architecture in an IC to provide controllability and observability of IC components. Scan testing of complex electronic systems and circuits often requires analysis of measurement points (e.g., appropriately selected circuit nodes) by applying test vectors to stimulate certain aspects of a circuit (e.g., a functional logic component). For example, microelectronic chips typically have numerous connections between functional logic components and these connections are often appropriate circuit nodes for testing fault isolation and detection. Usually the greater the test coverage the greater the capacity of a scan test system and method to detect faults. However, not all features of an IC (e.g., connection nodes, functional logic components, etc.) are necessarily compatible with scan test mode operations.
Features on some integrated circuits react adversely to certain scan test vectors and do not offer a sufficient level of scan test operation predictability. For example, scan test cells usually include registers that are utilized for both normal operations and scan test operations and there is a potential for some scan test vectors to trigger inappropriate operations in the functional components if certain scan test vectors are shifted into the registers. In particular, functional logic associated with driving connections to a bus typically has a potential to create bus access conflicts during scan testing. For example, a bus driver that receives an output enable signal via a scan test cell will cause a bus driver to violate bus access constraints if an inappropriate signal is inadvertently forwarded during scan testing. Often there are difficulties in predicting the number of drivers of an IC that may be activated by some scan test vectors in a typical scan test system. More than one driver becoming active at the same time results in adverse bus access contention conditions and such bus contentions typically lead to a circuit failure.
FIG. 1 is a block diagram of a bus driver system 100. Bus driver system 100 comprises tri-state bus drivers 111 through 118, scan test cells 130 through 143, and bi-directional buses 105 and 107. Scan test cells 130 through 133 are coupled to tri-state bus drivers 111 through 114 respectively and scan test cells 140 through 143 are coupled to tri-state bus drivers 115 through 118 respectively. Bus 105 is coupled to scan test cells 130 through 133 and scan test cell 140. Bus 107 is coupled to scan test cells 140 through 144 and scan test cell 130. Bus 105 and 107 provide a communication path between components of bus driver system 100. Bus drivers 111 through 114 drive signals onto bus 105 and bus drivers 115 through 118 drive signals onto bus 107. Scan test cell 130 through 133, transmit output enable (OE) signals that activate bus drivers 111 through 113 respectively and scan test cells 140 through 143 transmit output enable (OE) signals that activate tri-state bus drivers 115 through 118 respectively. Scan test cells 130 through 143 are also utilized during scan test operations to transmit and capture scan test signals.
Serial test vectors shifted via scan test cells 130 through 143 during scan test operations can cause multiple bus drivers to attempt a bus access at the same time during a capture cycle of the scan test. During normal operations, scan test cells 130 through 143 function as registers that transmit output enable signals to bus drivers 111 through 118. Bus drivers 111 through 118 drive signals onto a bus in response to an appropriate signal from a bus driver scan test cell. During a scan test operation, scan test cells 130 through 143 function as scan test cells that shift scan test signals during a shift cycle and capture information during a capture cycle. A bus access contention problem arises during a capture cycle if the appropriate activation information is coincidentally shifted into multiple scan test cells that provide output enable signals to different bus drivers and the activation information is residing in a register of those scan test cells during a scan test capture cycle. For example, scan test cell 131 and scan test cell 133 normally transmit a logical 1 value to activate bus driver 112. During a scan test, if a test vector shifted into scan test cell 131 and scan test cell 133 includes a logical 1 value and the logical 1 value is present in scan test cells 131 and 133 during a capture cycle, then both tri-state bus drivers 112 and 114 will attempt to drive information on bus 105 at the same time causing a bus access conflict.
Some systems attempt to limit potential bus conflicts during scan testing by eliminating some scan test coverage. In some bus driver systems tri-state bus drivers are hardcoded or hardwired to limit activation of only one specific bus driver during the entire scan testing and that particular bus driver does not change. For example, bus driver 111 may be hardcoded to access bus 105 during a scan test operation and the remaining bus drivers coupled to bus 105 (e.g., bus drivers 112 though 114) are hardcoded to prevent them from accessing bus 105 during scan testing. Thus, the ability of the remaining bus drivers coupled to bus 105 (e.g., bus drivers 112 though 114) to drive a signal onto bus 105 can not be tested during scan testing. In another example some bus driver systems xe2x80x9ctri-statexe2x80x9d all the tri-state bus drivers during scan testing or otherwise limit the use of a tri-state bus in situations involving scan testing. In these situations, scan test coverage is lost as a result of either hardcoding to limit bus driver activation to one particular bus driver or tri-stating all the bus drivers during scan testing. In particular the ability to adequately scan test the bus driver components (e.g., bus drivers 111 through 118) is limited because all the bus drivers are not able to fully participate in the scan testing. Without the ability to appropriately control inputs to bus drivers and observe outputs, the bus drivers can not be adequately tested to determine if they are functioning correctly.
FIG. 1A is a mask diagram of a bus driver system 10A. Bus driver system 100A is similar to bus driver system 100 except scan test cell 140A and scan test cell 130A are coupled directly to bus 105 and bus 107 respectively. Thus, information is not latched between bus 105 and bus 107 when it is communicated over the bridges between bus 105 and 107. If bus driver 115A and 111A are both enabled at the same time, information can inappropriately loop around the bridges between bus 105 and bus 107. Thus, if logical values of a scan test vector is shifted into scan test cell 140A and scan test cell 130A that coincidentally match logical values of an asserted scan test driver enable signal, then an inappropriate looping of information around the bridges between bus 105 and 107 occurs. This inappropriate looping may lead to unknown or indeterminate values which result in reduced fault coverage.
What is required is a system and method that facilitates flexible scan testing of bus drivers. The system and method should permit a designer to efficiently and effectively scan test the system without permanently losing scan test coverage of a bus driver. The system and method should permit a selection of different bus drivers to participate in scan test operations while diminishing the probability of a test vector will cause a bus access conflict during a capture cycle. The system and method of the present should also facilitate the avoidance of information inappropriately looping through bridges between busses.
The present invention reduces adverse impacts on functional components during scan test operations due to coincidential effects associated test vector values by facilitating flexible restriction of output transmissions from chosen scan test cells. The system and method of the present invention permits selected masking of different scan test cell outputs, resulting in greater control of scan test operations and improved observability without permanently losing scan test coverage of a scan test cell. The system and method of the present invention permits efficient and effective scan testing of a system while diminishing the probability of a test vector creating adverse conditions for functional components.
In one embodiment of the present invention, a scan test cell restriction system facilitates appropriate scan testing of a bus driver system by permitting flexible masking of bus driver enable signals during scan test operations. A scan test cell masking component selectively masks an output transmission of a scan test cell from reaching a functional component of the bus system. The scan test cell masking component masks logical values shifted into the scan test cell during a shift cycle from being communicated during a capture cycle of a scan test operation to a functional component coupled to the output of the scan test cell. The present invention reduces the risk of coincidental adverse affects associated with a test vector shifted into a scan test cell that feeds enabling signals into a bus driver. The scan test cell masking component is activated by a scan test cell output selection component and by varying selected scan test cell masking components variety of bus drivers participate in testing operations one at a time.